1. Field of the Invention
This invention relates to a digital FM demodulating apparatus and, more particularly, to a digital FM demodulating apparatus used in a VTR.
2. Description of the Related Art
As is well known, a conventional digital FM demodulating apparatus, e.g., a digital FM demodulating apparatus used in a VTR (viedo tape recorder) is arranged as shown in FIG. 1. That is, an input video signal is supplied to recording signal processor 12 consisting of an FM modulator and the like. An output from processor 12 is supplied as a digital FM signal to input terminal 16 of digital FM demodulating apparatus 14. The digital FM signal, e.g., signal Asin .theta. is supplied to phase shift circuit 18 to be divided into digital FM signal Asin .theta. and signal Acos .theta. which is phase-shifted from signal Asin .theta. through 90.degree.. Thereafter, signals Asin .theta. Acos .theta. are supplied to absolute value circuits 20 and 22 to be converted into absolute value signals .vertline.Asin .theta..vertline. and .vertline.Acos .theta..vertline., respectively. Then, divider 24 performs the following division using the absolute value signals: EQU .vertline.Asin .theta..vertline./.vertline.Acos .theta..vertline.=.vertline.tan .theta..vertline.
Division result .vertline.tan .theta..vertline. obtained by divider 24 is address data of ROM (read-only memory) 26 which stores a tan.sup.-1 conversion table. For this reason, ROM 26 outputs phase data .theta. falling within the range of 0 to .pi./2. Data .theta. is supplied to phase expanding circuit 28 to be converted into phase data .theta.' falling within the range of -.pi. to .pi. on the basis of a pair of digital FM signals Asin .theta. and Acos .theta. output from circuit 18.
Thereafter, data .theta.' is supplied to differentiating circuit 30 comprising delay circuit 30a for delaying one cycle of a sampling clock of input digital FM signal Asin .theta. and subtracter 30b, thereby performing the following calculation: EQU .theta..sub.2 '-.theta..sub.1 '=tan.sup.-1 x.sub.2 -tan.sup.-1 x.sub.1
As a result, signal data (d.theta.'/dt) obtained by differentiating data .theta.' by time t is output from output terminal 32.
In the conventional digital FM demodulating apparatus having the above arrangement, however, if signal Asin .theta. is represented by an 8-bit complement of 2, an address of ROM 26 requires 21 bits in order to set precision at the output side of ROM 26 to correspond to 11 bits. For this reason, the capacity of ROM 26 must be: EQU 2.sup.21 .times.11=23 megabits
That is, the scale of ROM 26 is increased to complicate and enlarge its arrangement. In addition, since ROM 26 is enlarged, its cost is also increased to pose a problem of economical disadvantage.